1. Field of the Invention
The present invention relates to bit line arrays for dynamic random access semiconductor memories, and more particularly to an interdigitated folded bit line architecture for memory cells.
2. Description of the Prior Art
U.S. Pat. No. 4,922,453, issued May 1, 1990 to Hidaka entitled BIT LINE STRUCTURE OF DYNAMIC TYPE SEMICONDUCTOR MEMORY DEVICE, discloses a semiconductor memory device of a folded bit line structure that comprises a plurality of bit line pairs in which each bit line pair is divided into a plurality of blocks along a longitudinal direction, and each divided bit line pair is formed by an interconnection layer at a level above a substrate different from the level of an adjacent divided bit line pair in the same block and different from the level of the same bit line pair in an adjacent block.
U.S. Pat. No. 4,807,017, issued Feb. 21, 1989 to Ema et al entitled SEMICONDUCTOR MEMORY DEVICE WITH WIRINGS HAVING ENSURED CROSS SECTIONS, discloses a memory cell matrix region of a semiconductor memory device such as a dynamic RAM or a static RAM wherein wirings of the same material are distributed between different layers in such a manner that the upper wirings overlap the lower wirings. Accordingly, the width of the wirings can be increased for a semiconductor memory device having a high concentration and high integration.
U.S. Pat. No. 4,977,436, issued Oct. 9, 1990 to Tsuchiya et al entitled HIGH DENSITY RAM, disclosed a high density DRAM having a plurality of cells each including a storage capacitor and a single control FET formed together in a trench to substantially reduce planar area of the cell. The FET drain is formed in the upper portion of a pedestal and is accessible externally through a metal line, which reduces line resistance and capacitance. Field oxide is included to isolate capacitors and reduce leakage and breakdown.
U.S. Pat. No. 4,962,476, issued Oct. 9, 1990 to Kawada entitled SEMICONDUCTOR MEMORY DEVICE HAVING BIT LINES LESS LIABLE TO HAVE INFLUENCES OF THE ADJACENT BIT LINES, discloses a semiconductor memory device that has a plurality of memory cells of the one-transistor and one-capacitor type, and a plurality of bit lines coupled to columns of the memory cells, respectively, and disposed in an insulating film over the memory cells, and a common upper electrode is shared by the storage capacitors of the memory cells and has shield portions interposed between the bit lines, so that the adjacent bit lines are less liable to be capacitively coupled by virtue of the shield portions, thereby allowing data bit signals to propagate without any undesirable influence of the adjacent bit lines.
U.S. Pat. No. 4,941,031, issued Jul. 10, 1990 to Kumagai et al entitled DYNAMIC MEMORY DEVICE WITH IMPROVED WIRING LAYER LAYOUT, discloses a structure wherein a signal line runs in parallel with first to fourth bit lines on a memory cell array of a dynamic memory device. The signal line runs between and along the first and third bit lines, turns at a predetermined position, turns again and runs between and along the second and fourth bit lines. The predetermined turning position is a position corresponding to the half of the bit line length. The result is that the stray capacitances between the signal line and these bit lines are equal.
U.S. Pat. No. 4,937,649, issued Jun. 26, 1990 to Shiba et al entitled SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A CAPACITOR FOR STABILIZING A VOLTAGE AT A POWER SUPPLYING WIRING, describes a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of logic gates formed in the semiconductor substrate, power source wiring and ground wiring formed on the semiconductor substrate to supply power source voltage to the logic gates and a capacitor formed on the semiconductor substrate and distributively connected between the power source wiring and the ground wirings.
U.S. Pat. No. 4,873,560, issued Oct. 10, 1989 to Sunami et al entitled DYNAMIC RANDOM ACCESS MEMORY HAVING BURIED WORD LINES, discloses a structure that relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the side-wall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate. U.S. Pat. No. 4,833,518, issued May 23, 1989 to Matsuda et al entitled SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED INTERCONNECTION STRUCTURE OF MEMORY CELL ARRAY, describes a structure wherein a memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell array.
U.S. Pat. No. 4,710,789, issued Dec. 1, 1987 to Furutani et al entitled SEMICONDUCTOR MEMORY DEVICE, discloses a semiconductor memory device wherein memory cells of a first column each comprising an N-channel FET are connected to a first bit line and memory cells of a second column each comprising a P-channel FET are connected to a second bit line. The first bit line and the second bit line are connected to complementary terminals of a sense amplifier to form a folded bit line pair. A word line is connected to the gate of the N-channel FET of one of the memory cells of the first column and to the gate of the P-channel FET of one of the memory cells of the second column. The word line is selectively provided with a first voltage to make conductive the N-channel FET connected thereto and to make nonconductive the P-channel FET connected thereto, or a second voltage to make conductive the P-channel FET connected thereto and to make nonconductive the N-channel FET connected thereto, or a third voltage to make nonconductive both the N-channel FET and the P-channel FET connected thereto.